(a) Field of the Invention
The present invention relates to a built-in self-test (BIST) circuit in a memory device and, more particularly, to a BIST circuit suitably used for an LSI that includes a logic circuit and a DRAM (dynamic random access memory) section.
(b) Description of a Related Art
Product test of a memory device such as a DRAM is generally conducted by using an external memory tester which includes a microprocessor for generating test patterns for testing the DRAM. The test patterns necessary to test the functions of the DRAM include column bars, checker board, marching, shifted diagonal test and other test patterns.
In the control by the column bars, the memory tester:
(1) stores xe2x80x9c1xe2x80x9d in the cells (or addresses) in odd numbered columns and xe2x80x9c0xe2x80x9d in the cells in even numbered columns,
(2) consecutively reads the data stored in each cell in the order specified, and
(3) iterating the storing and reading the data by exchanging data xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d in each memory cell.
In the control by the checker board, the memory tester:
(1) stores xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d in the cells alternately in odd numbered columns and stores xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d in the cells in even numbered columns,
(2) reads the data stored in each cell in the order specified, and
(3) iterating the storing and reading the data by exchanging data xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d in each memory cell.
In the control by the marching, the memory tester:
(1) stores xe2x80x9c0xe2x80x9d in all the cells,
(2) reads the data stored in each cell in the order specified, and then stores xe2x80x9c1xe2x80x9d in all the cells,
(3) reads the data stored in the cells in the reversed order, and stores xe2x80x9c0xe2x80x9d in all the cells, and
(4) iterating the reading and storing the data by exchanging data xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d in each memory cell.
There are problems in the product test of the DRAM by using the memory tester for a large number of test patterns, as follows. First, when a system LSI including a logic circuit and a DRAM section is to be tested, both a logic tester and a memory tester are required, which increases the test time to raise the costs for the test operation as well as the cost for the testers. If a tester having a function for testing both the logic circuit and the DRAM section at a time and with a high speed is used for the system LSI, the cost for the tester further increases.
In view of the above problems, a system LSI having a BIST circuit is particularly noticed. The BIST circuit in the system LSI includes both a test pattern generator and a data comparison section. The test pattern generator responds to a test instruction signal for generating test patterns for storing test data in memory cells, whereas data comparison section compares the data read out from the memory cells against the expected data obtained by logical simulation of the normal LSI to judge the pass/fail of the DRAM in the system LSI.
The BIST circuits are categorized into two different systems including a micro-instruction control system, such as described in JP-A-10-69799 and a hardware control system, such as described in JP-A-61-54550, -63-4500 and -8-100536. The micro-instruction control system includes a built-in ROM for storing micro instructions specifying the self test, and has an advantage of design choice.
The micro-instruction control system requires a process for fabricating a ROM section in addition to the processes for fabricating the logic circuit and the DRAM section, which involves a larger circuit scale and higher costs of the system LSI. In addition, in order for testing all the functions of the DRAM as in the case of using an external memory tester, it is necessary to enlarge the circuit scale of the micro-instruction control system, because current micro-instruction control system cannot test the DRAM for all the test patterns.
In the hardware control systems described in the above publications, only the test using the checker board pattern or the patterns modified from the checker board pattern can be executed. Thus, all the desired functions of the DRAM cannot be tested.
It is therefore an object of the present invention to provide a BIST circuit provided in a DRAM, which is capable of providing a large number of test patterns for the DRAM and thus testing substantially all the functions or any desired functions of the DRAM, and being manufactured in a simple structure.
The present invention provides a built-in self-test (BIST) circuit in a DRAM including a test mode generator for responding to a first signal to select one of a plurality of test modes, a test signal generator for generating a plurality of test control signals based on the selected one of the test modes, an address counter for generating a sequence of addresses based on the selected one of the test modes, a test execution section for executing a test of memory cells specified by the sequence of addresses based on the test control signals, the test execution section outputting the first signal after the memory cells specified by the sequence of addresses are tested based on the selected one of the test modes.
In accordance with the BIST circuit of the present invention, any combination of test patterns can be generated by selecting the configuration of the test signal generator in the BIST circuit having a simple structure.